1. Field of the Invention
The present invention relates to transistor switches. More particularly, the present invention relates to a high power transistor switch with low transmission loss.
2. Description of the Related Art
For acquiring superior operation performance, field-effect transistors, hereinafter FETs, have been widely utilized to realize conventional single-pole double-throw switches. Referring to FIG. 1, a conventional single-pole double-throw switch realized by field-effect transistors is schematically illustrated. The conventional switch is constituted by a pair of FETs T.sub.1 and T.sub.2. In FIG. 1, reference numeral 16 designates an antenna whereas Rx represents a receiving terminal through which received signals are sent to a demodulator (not shown in the drawing) for further processing, and Tx represents a transmitting terminal through which signals to be transmitted from a modulator (not shown in the drawing) are sent to the antenna 16.
As shown in FIG. 1, both the FETs T.sub.1 and T.sub.2 are configured with sources connected with a bias circuit 10, wherein a capacitor C.sub.1 is provided between the source of the FET T.sub.1 connected to the bias circuit 10 and the transmitting terminal Tx, and another capacitor C.sub.2 is provided between the source of the FET T.sub.2 connected to the bias circuit 10 and the receiving terminal Rx. Moreover, the drains of the FETs T.sub.1 and T.sub.2 are both coupled to the antenna 16 by a capacitor C.sub.3. The capacitors C.sub.1, C.sub.2 and C.sub.3 are all DC blocking capacitors. In addition, the FET T.sub.1 has its gate connected to a first voltage source 12 through a resistor R.sub.1, whereas the FET T.sub.2 has its gate connected to a second voltage source 14 through a resistor R.sub.2.
In transmission mode, since the FET T.sub.1 is turned on and the FET T.sub.2 is turned off, signals to be transmitted go from the transmitting terminal Tx through the FET T.sub.1 to the antenna 16. In reception mode, on the other hand, signals received from the antenna 16 pass through the FET T.sub.2 to the receiving terminal Rx while the FET T.sub.1 is turned off and the FET T.sub.2 is turned on.
However, the FET T.sub.2 in the reception path may be erroneously turned on and result in a great deal of transmission loss when the conventional transistor switch is operated during high power transmission. Referring to FIG. 2, a drawing for explaining transmission loss occurring to the conventional transistor switch because the FET T.sub.2 is erroneously turned on is schematically illustrated. As mentioned above, the FET T.sub.2 should be turned off while the FET T.sub.1 is turned on in the transmission mode. The FET T.sub.1 and T.sub.2 are preferably fabricated onto compound semiconductor material and provided with a threshold voltage of about -0.6V; that is, the FET device is turned on when V.sub.gs &gt;-0.6V and turned off when V.sub.gs &lt;-0.6V. As an example, in the transmission mode, the first voltage source 12 and the second voltage source 14 supply 3V and 0V, respectively, whereas the bias circuit 10 provides 3V to the FET T.sub.2. Accordingly, the signals to be transmitted pass through the FET T.sub.1 and the capacitor C.sub.3 to the antenna 16.
For example, the voltage at the node V.sub.D ranges 3V.+-.6V under high power transmission. There are two junction capacitors C.sub.gd and C.sub.gs (the capacitance of C.sub.gd and C.sub.gs are usually less than 1 pF) between the gate-drain and gate-source of the FET T.sub.2, respectively. Assuming that the capacitors C.sub.gd and C.sub.gs are of substantially equal capacitance, the gate voltage V.sub.G of the FET T.sub.2 ranges within 0V.+-.3V along with the V.sub.D variation because of the coupling effect.
When V.sub.D attains the maximum voltage, for example, 9V (3V+6V), the gate voltage V.sub.G of the FET T.sub.2 is about 3V (0V+3V). Thereby, the highest value for the voltage difference between V.sub.G and V.sub.S is 0V, which is higher than the threshold voltage of the FET T.sub.2 (e.g., -0.6V), and therefore, the FET T.sub.2 is erroneously turned on in transmission mode. Alternatively, when V.sub.D attains the minimum voltage, for example, -3V (3V-6V), the gate voltage V.sub.G of the FET T.sub.2 is about -3V (0-3V). Thereby, the highest value for the voltage difference between V.sub.G and V.sub.D is 0V, which is higher than the threshold voltage of the FET T.sub.2 (e.g., -0.6V), and, therefore, the FET is erroneously turned T.sub.2 on in transmission mode. Accordingly, the FET T.sub.2 may be erroneously turned on during either the positive cycle or the negative cycle so as to cause loss to the transmission power along the reception path.
For reducing the coupling effect, two FETs connected in series instead of the FET T.sub.2 may be a feasible approach. However, the series-connected FETs will increase loss along the reception path under reception mode and deteriorate reception sensitivity. Moreover, more FETs are required to implement the transistor switch.